Portable embedded systems have become increasingly popular over the past few years. Personal digital assistants, pocket computers, mobile phones, digital cameras and GPS based portable navigation systems are some of the examples. These systems have inherent limitations in terms of their energy requirements, size, weight, cost and processing power. Since batteries are finite sources of energy, with varying and limited opportunities of getting recharged, it becomes necessary to manage the battery energy aggressively. In this work we concentrate on Portable Reconfigurable Computing Platforms which either have Field Programmable Gate Arrays (FPGA) as their main processing element or have a heterogeneous mix of embedded processors, voltage scalable processors and FPGAs. For these systems we propose and study different architectures, methodologies and algorithms which enable us to make better decisions for achieving a trade-off between battery consumption and performance. We first focus on platform level battery-efficiency and then by extending the tools and methodologies developed for individual platforms to a network of these systems we have studied network wide battery-efficiency for a sensor network.; As a part of platform level work we present a technique in which a single task is executed using a combination of cores instead of a single one, and show that by running a combination of cores it is possible to prolong the battery life or the number of calculations performed, depending upon the goal. We also introduce the concept of reconfigurable tiles and present a methodology which is based on the idea that by changing the active area of an FPGA significant battery savings are possible. Further, we present an iterative, heuristic algorithm for battery aware task sequencing and implementation-option (design-point) allocation for single and multiple processing unit execution. We have developed and used, as a hardware testbed, a portable reconfigurable platform called iPACE-V1, which we will also describe briefly. We have also studied the effects of battery-efficient execution on a sensor network with reconfigurable nodes and have shown that the total network lifetime can be increased many times by the use of RC based nodes as compared to traditional fixed processor based nodes. Finally, we present some directions where this work can be extended.
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