A 20kHz Frequency Resolution DCO.

摘要

This thesis presents a Digitally Controlled Oscillator (DCO) design and implementation with its fine tuning band controlled by a Dynamic Element Matching (DEM) technique. All the components of the system are designed in 0.13mum IBM technology. The DCO output frequency ranges from 108MHz to 135MHz. The coarse tuning has 256 tuning levels and the fine tuning has 32 tuning levels resulting in an 8192 level (256 x 32) capacitance selection. The relative process variations that define the capacitors' discrepancies from each other on the same chip are between 0.2% and 0.5% of the absolute capacitor value. These discrepancies have a significant effect on the frequency resolution, especially for small capacitor steps. The proposed DEM technique reduces the process variations and mismatches in the small capacitor deltas used for fine tuning. The measurement results show that a 20kHz frequency resolution can be achieved over process variations. It is proved that the output frequency resolution is improved by dithering among different capacitor groups. The DCO core consumes 1.455mA current from a 1.185V voltage supply. The capacitor dithering introduced extra phase noise to the oscillator. Far out phase noise introduced by dithering cannot be filtered out by a PLL.