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Lab-on-a-Chip design automation.

机译:芯片实验室设计自动化。

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A Lab-on-a-Chip (LoC) is essentially a miniaturized microchip implementation of an analytical chemistry laboratory. LoC's that are fast, accurate, automatable and inexpensive to fabricate have been used in the life-science and biomedical industries for applications in genomics, drug discovery, point-of-care analysis and in-vivo diagnostics. Microscale unit operations such as mixing, reaction and separation have been constructed entirely on-chip. In this thesis we present a model-based methodology for automatically designing complex LoC channel systems using large-scale optimization and computer-aided design techniques.; LoC design combines complex physiochemical phenomena with challenging chip layout and channel interconnectivity issues. The chemistry that takes place during chip operation, as well as the chip layout and manufacturing process must be understood so that the appropriate design trade-offs and constraints are considered. Channel geometry, and the system's channel topology have been shown to contribute a great deal to the overall performance of the final LoC design [1]. These issues result in a design problem that is highly nonlinear and highly combinatorial.; Currently, most LoC design involves time consuming laboratory experiments or iterative simulation using computational fluid dynamics (CFD) or finite element modeling packages [2]. While these approaches are excellent for design verification, they are inefficient for design optimization. Reduced order system simulation approaches have been developed, but these methods rely on black-box simulators that are difficult to automate. Some simple shortcut methods for specific LoC unit operations have been presented, however, they lack the generality required for complete system level LoC design. Here we develop the tools necessary to reduce the LoC design cycle from months to only minutes. This thesis covers five major topics: (1) The physical analysis and conceptualization of chip-based unit operations is described in chapters 2 and 3. In these chapters we show how to decompose LoCs into a library of canonical subsystems that share an interconnection interface [3, 4]. (2) In chapter 3, we describe our efficient reduced-order system simulation framework that combines Kirchoffian network analysis and topological sorting from electrical circuit simulation with stream tearing and the sequential-modular structure of process flowsheet simulation [5]. (3) The creation of single and multi-objective nonlinear programming formulations for the optimal design of LoC subsystems [4, 6] and multifunction LoCs is described in chapters 4, 5 and 7. (4) The development of a rigorous General Disjunctive Programming (GDP) [7] formulation for the optimal design of multiplexed LoCs, as well as a more tractable combinatorial formulation [8] is discussed in chapter 6. (5) Efficient tailored solution algorithms to solve our single subsystem formulations are describe in chapter 4 [4]. In chapter 6, Very Large Scale Integration (VLSI) circuit design, iterative heuristics and traditional optimal design techniques are adapted to design complex LoCs [8].; We demonstrate our methodology by automatically designing both single system and multiplexed capillary electrophoresis LoC's. We also address the simulation and optimization of multifunction LoCs that incorporate mixing, reaction, injection and separation processes. We design and optimize an LoC based immunoassay to demonstrate this work. We compare our designs to experimental designs from the literature and designs generated using CFD tools. Finally, we conclude by proposing critical areas for future research and development in this field.
机译:芯片实验室(LoC)本质上是分析化学实验室的微型芯片实现。 LoC快速,准确,可自动化且制造成本低廉,已用于生命科学和生物医学行业,用于基因组学,药物发现,即时护理分析和体内诊断。诸如混合,反应和分离之类的微型单元操作已完全在芯片上构建。在本文中,我们提出了一种基于模型的方法,该方法使用大规模优化和计算机辅助设计技术来自动设计复杂的LoC信道系统。 LoC设计将复杂的物理化学现象与具有挑战性的芯片布局和通道互连问题结合在一起。必须了解芯片操作期间发生的化学反应以及芯片布局和制造过程,以便考虑适当的设计折衷和约束。通道的几何形状和系统的通道拓扑已显示出对最终LoC设计的整体性能有很大贡献[1]。这些问题导致了高度非线性和高度组合的设计问题。当前,大多数LoC设计都涉及耗时的实验室实验或使用计算流体力学(CFD)或有限元建模软件包的迭代仿真[2]。尽管这些方法对于设计验证非常有效,但对于设计优化却效率不高。已经开发了降阶系统仿真方法,但是这些方法依赖于难以自动化的黑盒仿真器。已经提出了一些用于特定LoC单元操作的简单快捷方法,但是它们缺乏完整的系统级LoC设计所需的通用性。在这里,我们开发了必要的工具,可以将LoC设计周期从几个月缩短到只有几分钟。本文涵盖五个主要主题:(1)第2章和第3章介绍了基于芯片的单元操作的物理分析和概念化。在这些章中,我们展示如何将LoC分解为共享互连接口的规范子系统库[ 3,4]。 (2)在第3章中,我们描述了有效的降阶系统仿真框架,该框架结合了基尔霍夫网络分析和电路仿真与流撕裂和过程流程图仿真的顺序模块化结构相结合的拓扑排序[5]。 (3)在第4、5和7章中介绍了用于LoC子系统[4、6]和多功能LoC的最佳设计的单目标和多目标非线性规划公式的创建。(4)严格的通用析取规划的发展(GDP)[7]用于优化LoC的最佳设计的公式,以及更易于处理的组合公式[8]在第6章中进行了讨论。(5)在第4章中描述了解决我们的单子系统公式的有效定制解决方案算法[4]。在第6章中,超大规模集成电路(VLSI)的电路设计,迭代启发法和传统的最佳设计技术适用于设计复杂的LoC [8]。我们通过自动设计单系统和多路毛细管电泳LoC展示了我们的方法。我们还解决了将混合,反应,进样和分离过程纳入其中的多功能LoC的仿真和优化。我们设计并优化了基于LoC的免疫分析方法,以证明这项工作。我们将我们的设计与文献和使用CFD工具生成的设计的实验设计进行比较。最后,我们最后提出了该领域未来研究和开发的关键领域。

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