Design and implementation of reconfigurable hardware for real-time particle filtering.

摘要

Particle Filtering is a Monte Carlo sampling based signal processing technique that is applied to systems described using dynamic state space models. For models that are non-linear and non-Gaussian, traditional filtering techniques fail in terms of filter performance. Particle filters can handle nonlinear and non-Gaussian systems much more efficiently than such methods. As a result, these filters have gained immense popularity in recent years. However, their high computational intensity, which is widely recognized in literature, makes them unsuitable for implementation on sequential platforms like DSPs. This fact, along with the absence of dedicated hardware for particle filtering has prevented their use in real time systems despite their suitability in terms of filter performance. The goal of this dissertation is to address this gap and develop hardware suitable to real time particle filtering. This research has progressed through the steps of algorithmic optimization, architecture development and physical implementation, and has produced the first FPGA prototype for a particle filter.;Flexibility of particle filters is another of their widely recognized assets. Within a general framework, the particle filter can be applied to a wide range of problems by simply modifiying certain filtering parameters. We exploit the concept of hardware reconfiguration to develop reconfigurable architectures, whereby the same particle filtering device can be used for different problems by simply specifying a set of parameters. We use a novel buffer controller based design methodology to develop a reconfigurable particle filtering hardware that can be easily tuned to the problem at hand. Run time reconfiguration for implementation of multiple model particle filters with dynamically changing model sets is also explored. For each of the hardware architecture proposed, an FPGA based evaluation of speed and resource requirement is performed and the overall improvements over a sequential DSP based implementation of the corresponding algorithm are analyzed.;With these contributions, this dissertation takes a significant step in enabling the application of particle filters to practical systems requiring real time processing.;Often, real world systems require multiple models for accurate and complete description. A class of particle filters known as Multiple Model Particle Filters are applied to such systems. Starting from the hardware developed for the basic particle filter, we propose a parallel, distributed architecture for implementation of a novel multiple model particle filtering algorithm. The distributed processing units of the architecture interact using a data exchange protocol with low interconnect requirement and no communication bottleneck. This high speed architecture with its immense scalability is well suited to practical problems that require a intensive particle filtering, incorporate a large number of models and have real time processing requriements. The proposed architecture implemented on an FPGA platform and applied to a practical problem, results in a speedup of upto 100 times over a DSP implementation.