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Efficient protocol verification using rule-based systems.

机译:使用基于规则的系统进行有效的协议验证。

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摘要

The increasing complexity of industrial hardware systems has brought into prominence the role of formal verification in the debugging and validation of their designs. While simulation based testing still has great value, the advantages and complementarity of formal verification are now beyond question. Automated verification techniques, especially, have proven to be highly effective. Verification techniques explore the entire state space of a design model and can often find elusive bugs that lurk in the corners of complex designs.; However, verification techniques suffer from the well-known state explosion problem. The large state spaces of complex designs continue to outgrow the capacity of verification techniques. Considerable progress has been made in recent years to enhance the capacities of automated verification tools, including the advent of binary decision diagram (BDD) and satisfiability solver (SAT) based symbolic techniques. Unfortunately, most of these techniques are driven by, and suited to, hardware verification. Many other classes of designs, such as communication protocols from different domains, and software systems, are not easily amenable to either description, or verification, or both, using these symbolic techniques.; This dissertation presents a set of techniques for increasing the power and reach of explicit state-enumeration verification tools for rule based systems, a convenient paradigm for protocol. The techniques have been implemented as extensions to the Murphi verifier, and have been tested on high-level protocol designs of varying sizes, with very promising results. First, we develop an efficient algorithm to perform partial order reduction, a powerful state space reduction technique, on rule-based systems. We then develop techniques to exploit common features of rule-based systems, such as parametricity, symmetry and the transactional nature of many designs, to achieve further state space reduction. Put together, these techniques have resulted in up to a 90% state space reduction.; Another contribution is the design of a translator from the rule-based language of Murphi into the input language of the symbolic model checking tool NuSMV. Based on symbolic simulation, this translator makes state-of-the-art symbolic techniques available to systems modeled in the high-level Murphi language.; As a result of these advancements, many complex systems can now be verified faster, and with much less memory.
机译:工业硬件系统日趋复杂,已使形式验证在其设计的调试和验证中的作用日益突出。尽管基于模拟的测试仍然具有巨大的价值,但是形式验证的优势和互补性现在已成为问题。尤其是自动验证技术已被证明是非常有效的。验证技术探索设计模型的整个状态空间,并且常常可以发现隐藏在复杂设计的角落的难以捉摸的错误。但是,验证技术遭受众所周知的状态爆炸问题。复杂设计的大型状态空间继续超出验证技术的能力。近年来,在增强自动验证工具的能力方面取得了可观的进步,包括基于二进制决策图(BDD)和基于可满足性求解器(SAT)的符号技术的问世。不幸的是,这些技术大多数都是由硬件验证驱动的,并且适合于硬件验证。使用这些符号技术,许多其他类别的设计(例如来自不同领域的通信协议和软件系统)不容易接受描述或验证,或两者兼而有之。本文提出了一套用于提高基于规则的系统的显式状态枚举验证工具的功能和范围的技术,这是一种方便的协议范式。该技术已实现为Murphi验证程序的扩展,并已在各种大小的高级协议设计上进行了测试,并取得了非常可喜的结果。首先,我们开发了一种有效的算法,可以在基于规则的系统上执行部分阶约简,一种强大的状态空间约简技术。然后,我们开发技术以利用基于规则的系统的共同特征,例如参数化,对称性和许多设计的事务性,以实现进一步的状态空间缩减。综合起来,这些技术已使状态空间减少了90%。另一个贡献是从Murphi的基于规则的语言到符号模型检查工具NuSMV的输入语言的转换器设计。基于符号仿真,该翻译器使先进的符号技术可用于以高级Murphi语言建模的系统。这些进步的结果是,现在可以更快速地验证许多复杂的系统,而内存却要少得多。

著录项

  • 作者

    Bhattacharya, Ritwik.;

  • 作者单位

    The University of Utah.;

  • 授予单位 The University of Utah.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 102 p.
  • 总页数 102
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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