On the FPGA implementation and performance analysis of a digital carrier synchronizer.

摘要

The evolutionary growth of digital communication has an acute impact on the digital integrated circuit (IC) design industry. Nowadays instead of ASICs (Application Specific Integrated Circuits), Field programmable gate arrays (FPGAs) are often employed to implement digital communication systems due to the speed, performance, reliability and flexibility. Digital communication systems such as modulation-demodulation and M-PSK require the use of carrier synchronization in phase and frequency. This work addresses the FPGA implementation and analysis of a Digital Carrier Synchronizer (DCS), which is a phase-locked loop (PLL), realized using digital circuits. This novel methodology highlights implementation promises towards some of the critical issues associated with the design of its analog counterpart, usually known as PLL. The principle function of this DCS is heavily dependent on the Numerically Controlled Oscillator (NCO) and the Loop Filter (LF). There are various methods to implement NCOs and LFs that are used in the architectural model of DCS. This research work examines the performance of two different NCOs and LFs realization in DCS for modem (modulator-demodulator) application using FPGA based design solutions. The methods presented are Look up Table (LUT) and Xilinx ROM based NCO in one hand, and 1st order and 2nd order based LF in the other hand. Each has its own merits and de-merits. A DCS mathematical model has been developed in order to analyze the stability of the design. Furthermore, the performance of this two implementations based on three performance metrics i.e. stability, locking-time and tracking range has been studied. From the analysis, Xilinx ROM based NCO with 2nd order LF performs better and are more suited for modem's DCS.