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The MAP Implementation in Logic Circuits for Soft-Decision Decoding of MTR Codes

机译:逻辑电路中用于MTR码软判决解码的MAP实现

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摘要

Maximum a posteriori (MAP) algorithm and decoding with min-max approximations in Boolean logic circuits, had been independently considered as soft-decision decoding methods for maximum-transition-run (MTR) codes. These two approaches are confirmed as quite valuable, enabling MTR decoder to handle soft-values in framework of iterative decoding. In this paper further research of these methods has been made and novel idea of MAP algorithm utilization into logic circuits, of new MTR soft-decision decoder, is presented. The proposed concept is considered with simple and well know rate 4/5 (2, k = 8) MTR code over E2PR4 magnetic recording channel. The non-log and log MAP implementation results with equal performance, while max-log version results with 1.6 dB of coding gain, for BER = 10-5.
机译:最大后验(MAP)算法和布尔逻辑电路中具有最小-最大近似值的解码已被独立地视为用于最大转换运行(MTR)码的软判决解码方法。确认这两种方法非常有价值,从而使MTR解码器能够在迭代解码的框架中处理软值。在本文中,对这些方法进行了进一步的研究,并提出了新的MTR软判决解码器将MAP算法应用于逻辑电路的新思路。在E2PR4磁记录通道上以简单且众所周知的速率4/5(2,k = 8)MTR码考虑提出的概念。对于BER = 10-5,非对数和对数MAP实现的性能相同,而最大对数版本的编码增益为1.6 dB。

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