Synthesis of functions and procedures in behavioral VHDL

摘要

VHDL procedures and functions greatly increase the power andnutility of the language for specifying designs. While these constructsnare being used extensively for modeling, most VHDL synthesis tools limitntheir synthesis to a single implementation style such as treating themnas a component. The authors evaluate four techniques for the synthesisnof procedures/functions and discuss their relative merits and demerits.nThey examine these implementation styles in the light of VHDL signalsnand wait statement semantics. The results of the various implementationnstyles are shown on several examples