Partitioning strategies within a distributed multilevel logicsimulator including dynamic repartitioning

摘要

Standard gate and switch level simulators are not capable ofnsimulating accurate behavior of certain properties of BiCMOS digitalncircuits such as bidirectionality and charge sharing. Therefore, thenparallelizing and mixing of timing level simulation and gate levelnsimulation within a multilevel simulator would provide an effectivenbalance between simulation speed and functional accuracy. The ability ofnthe simulation system to change its internal partitioning duringnsimulation time is presented. This feature is called dynamicnrepartitioning and improves the speedup of parallel logic simulationnabout 20-40% using small numbers of subsimulators