Cell area minimization by transistor folding

摘要

Tall transistors can be folded into shorter ones to reduce thenlayout area. The authors take two rows of transistors, one for P-typentransistors and the other for N-type transistors, and attempt tondetermine an optimal folding for each transistor to minimize the layoutnarea. They present an O(K³L³) time transistornfolding algorithm to minimize the layout area, where K is the number ofnimplementations of each transistor due to folding, and L is the channelnlength