A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture

摘要

Heterogeneous multicore architectures, integrating several kinds of accelerator cores in addition to general purpose processor cores, have been attracting much attention to realize high performance with low power consumption. To attain effective high performance, high applica tion software productivity, and low power consumption on heterogeneous multicores, cooperation between an architecture and a parallelizing com piler is important. This paper proposes a compiler cooperative hetero geneous multicore architecture and parallelizing compilation scheme for it. Performance of the proposed scheme is evaluated on the heteroge neous multicore integrating Hitachi and Renesas' SH4A processor cores and Hitachi's FE-GA accelerator cores, using an MP3 encoder. The het erogeneous multicore gives us 14.34 times speedup with two SH4As and two FE-GAs, and 26.05 times speedup with four SH4As and four FE GAs against sequential execution with a single SH4A. The cooperation between the heterogeneous multicore architecture and the parallelizing compiler enables to achieve high performance in a short development period.