An approach to scheduling and allocation using regularityextraction

摘要

The authors propose that an important class of VLSI systems thatnare characterized by regularity of their descriptions can be efficientlynsynthesized in a hierarchical fashion. In other words, the regularityncan be extracted to abstract the system design, thereby simplifying thencomplex tasks of behavioral synthesis. Heuristics that extractnregularity and explore the design space in a hierarchical fashion arenpresented and the feasibility of the approach on signal processingnsystems is demonstrated. Extension of the proposed approach to othernsynthesis tasks is being investigated