首页> 外文会议>Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009 >21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber
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21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

机译:21.7在65nm CMOS中的500mW数字校准AFE,用于通过背板和多模光纤的10Gb / s串行链路

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The demand for bandwidth has fueled the deployment of 10 Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10 GBase-MMF) which were originally intended for much lower data rates. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes. This work describes a 65 nm CMOS AFE integrated in a DSP-based PHY for 10 Gb/s KR/MMF applications.
机译:带宽需求推动了10Gb / s流量在传统数据链路(例如串行背板(10GBase-KR)和多模光纤(10 GBase-MMF))上的部署,这些数据本来旨在降低数据速率。在严重的信道损伤下,基于DSP的收发器可提供强大的性能,并实现随过程的功率/面积扩展。这项工作描述了在基于DSP的PHY中集成的65 nm CMOS AFE,适用于10 Gb / s KR / MMF应用。

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