首页> 外文会议>Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International >An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression
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An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

机译:具有通道间干扰抑制功能的8Gb / s / pin 4pJ / b / pin Single-T-Line双(base + RF)波段同步双向移动存储I / O接口

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The demand for higher power efficiency and bandwidth is increasing as mobile devices keep enhancing its graphic computing and media processing capabilities. Current memory interfaces with single-wire signaling operate at 5Gb/s/pin [1] and 6Gb/s/pin [2] with the power efficiency of 17.4pJ/b/pin and 15.8pJ/b/pin, respectively. Mobile DDR memory I/O with differential signaling has better power efficiency of 6.4pJ/b/pin [3], and so does the prior dual-band interconnect (DBI) [4] with the efficiency of 5pJ/b/pin at 4.2Gb/s/pin for simultaneous bidirectional (SBD) mobile memory I/O interface. However, DBI's differential signaling is incompatible with existing standards, and it also occupies large die area for using differential transmission lines and an LC-oscillator for generating RF-carrier. To alleviate these concerns, we propose to use a Single-Transmission-Line DBI (STL-DBI) with the best figure-of-merit (FoM) defined as data rate per pin divided by the I/O-interface die area and power consumption.
机译:随着移动设备不断增强其图形计算和媒体处理能力,对更高能效和带宽的需求正在增长。当前具有单线信号传输的存储器接口以5Gb / s / pin [1]和6Gb / s / pin [2]运作,功率效率分别为17.4pJ / b / pin和15.8pJ / b / pin。带有差分信号的移动DDR存储器I / O具有6.4pJ / b / pin的更好的电源效率[3],现有的双频互连(DBI)[4]在4.2时的效率为5pJ / b / pin的情况也是如此。 Gb / s / pin,用于同时双向(SBD)移动存储器I / O接口。但是,DBI的差分信号与现有标准不兼容,并且在使用差分传输线和LC振荡器生成RF载波时也占用了较大的裸片面积。为了减轻这些担忧,我们建议使用单传输线DBI(STL-DBI),其最佳品质因数(FoM)定义为每个引脚的数据速率除以I / O接口芯片面积和功率消费。

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