Implementation of a fully pipelined BCD multiplier in FPGA

摘要

Decimal multiplication is one of the most frequently used operations in financial, scientific, commercial and internet-based applications. This paper presents an efficient implementation of a fully pipelined decimal multiplier designed with Carry Save Addition and coded into a reduced group of BCD-4221. This design is based on multiplier operands recoded in Signed-Digit radix-10, a simplified partial products generator, and decimal adders. A variety of multipliers architectures are processed on a Virtex-6 FPGA device. Several assessments are carried out in various N by M multiplications and their respective synthesis results show slightly optimistic figures in terms of area and delay in regard to some previously published works.