Adapting a low complexity datapath to MIPS-1

摘要

This paper presents the process of implementation of the MIPS-1 ISA on a simple didactic processor, without increasing the datapath complexity. This implementation may be desirable for academic purposes or for the use of datapaths of different complexity and performance in the MPSoC (Multiprocessor System-on-Chip) design. This paper shows the physical changes needed in the target datapath to fit the features of the new ISA. The techniques used to maintain the datapath simplicity are also shown. Finally, we present a simple implementation example used to validate this datapath, with simulation and synthesis results on FPGA.