Adder-Based Address Generation for Embedded MBIST

摘要

Today's System on Chips (SoC) are undoubtedly memory dominant, and it is predicted that the amount of space they occupy on the die will continue to increase, reaching up to 70 % by 2017. Built in self-test (BIST) has been the traditional technique for testing embedded memories over the years. Traditional BIST circuitry includes counter-based address generator which can be replaced by Adder-based address generator. The Adder-based address generator includes simple adder circuit to generate address and data for embedded MBIST. In this paper, adder-based address generator logic in BIST controller is proposed. This new idea for generating address and data has resulted in reduced area occupied by 40-68 % and the power dissipation by 83-86 % when compared with the traditional implementations.