A 12bit medium-time analog storage device in a CMOS standard-process

摘要

A new 12bit medium-time analog storage device is presented. The proposed circuit is based on a fully differential two-stage operational amplifier (OPAMP) working as Sample and Hold circuit (S&H). A novel refresh-scheme employing Common-Mode-Rejection has been developed which extends the storage time on a capactiance beyond the border of voltage decay caused by charge leaking. Measurements show 12bit and 8bit resolution for 15s and 330s respectively. The circuit is intended for use in Analog Neural Networks. The basic idea can be extended to design simple low-cost S&H circuits.