A high accuracy DAC designed with low offset follower structure

摘要

A high accuracy DAC circuit structure built into SAR ADC is proposed, the weighted network of this DAC adopts piecewise combination to reduce the power consumption, the follower behind the weighted network employs a two-stage amplifier with fold-cascode structure and switch capacitance compensation to decreasing offset error. Using Cadence Spectre simulation tools to analyze the circuit based on CSMC 0.35um CMOS technology, the results show that the maximum INL (integral nonlinearity) of the DAC is -0.34LSB, the maximum DNL (differential nonlinearity) is -0.18LSB, the power consumption of the whole module is 1.17mW, FoM(Figure of Merit) was 12.3, occupy the chip area is 0.208mm2. This is a good way to meet the requirements of low power consumption and high accuracy of SAR ADC.