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Torc: Towards an Open-Source Tool Flow

机译:Torc:迈向开源工具流程

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摘要

We present and describe Torc-Tools for Open Reconfig-urable Computing-an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://torc.isi.edu. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration. The Torc infrastructure can (1) read, write, and manipulate generic netlists-currently EDIF, (2) read, write, and manipulate physical netlists-currently XDL, and indirectly NCD, (3) provide exhaustive wiring and logic information for commercial devices, and (4) read, write, and manipulate bitstream packets (but not configuration frame contents). Tore furthermore provides routing and unpacking tools for full or partial designs, soon to be augmented with BLIF support, and with packing and placing tools. The architectural data for Xilinx devices is generated from non-proprietary XDLRC files, and currently supports 140 devices in 11 families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex4, Virtex5, Virtex6, Virtex6L, Spartan3E, Spar-tan6, and Spartan6L. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures.
机译:我们介绍并描述了用于开放可重配置计算的Torc-Tools,这是一种开放源代码的基础结构和工具集,完全以C ++源代码提供,可从http://torc.isi.edu获得。 Torc适用于定制研究应用程序,CAD工具开发以及体系结构探索。 Torc基础架构可以(1)读取,写入和操作通用网表,当前为EDIF;(2)读取,写入和操作物理网表,当前为XDL,以及间接的NCD;(3)为商用设备提供详尽的接线和逻辑信息,以及(4)读取,写入和操作位流数据包(但不读取配置帧内容)。此外,Tore还提供了用于全部或部分设计的布线和拆包工具,不久将通过BLIF支持以及打包和放置工具进行扩充。 Xilinx设备的体系结构数据是从非专有XDLRC文件生成的,目前支持11个系列的140个设备:Virtex,Virtex-E,Virtex-II,Virtex-II Pro,Virtex4,Virtex5,Virtex6,Virtex6L,Spartan3E,Spar -tan6和Spartan6L。我们相信,如果有必要的数据,Altera的体系结构和设计也可以得到类似的支持,并且我们已经成功地在内部使用了Torc和自定义体系结构。

著录项

  • 来源
  • 会议地点 Monterey CA(US);Monterey CA(US)
  • 作者单位

    Information Sciences Institute University of Southern California 3811 N Fairfax Dr, Ste 200 Arlington, VA 22203;

    Information Sciences Institute University of Southern California 3811 N Fairfax Dr, Ste 200 Arlington, VA 22203,Department of Electrical Engineering University of Washington 185 Stevens Way Seattle, WA 98195;

    Information Sciences Institute University of Southern California 3811 N Fairfax Dr, Ste 200 Arlington, VA 22203,Dept of Electrical and Computer Engenering University of Wisconsin-Madison 1415 Engineering Drive Madison, WI 53706;

    Dept of Electrical and Computer Engeneering Virginia Tech 302 Whittemore Hall Blacksburg, VA 24061;

    Dept of Electrical and Computer Engeneering Virginia Tech 302 Whittemore Hall Blacksburg, VA 24061;

    Information Sciences Institute University of Southern California 3811 N Fairfax Dr, Ste 200 Arlington, VA 22203;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 程序设计、软件工程;程序设计、软件工程;
  • 关键词

    C++; FPGA; place; route; unpack; EDIF; XDL; XDLRC;

    机译:C ++; FPGA;地点;路线;打开包装EDIF; XDL; XDLRC;

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