Sams

摘要

The issues behind the "memory wall" have existed for quite some time now, with realistic solutions still not available in modern processors. While the multicore approach will presumably fulfill the performance increase expected from Moore's Law in the near future, slow memory access will continue to remain a big obstacle and have a significant impact on the performance of applications. Even if a very fast path to off-chip memory was available, the optimal connection and hierarchical configuration of on-chip execution units and buffers would remain an open question, especially for general-purpose hardware. The goal of the workshop is to present latest research in how to overcome the problem of slow memory access with regard to an increasing number of cores on a chip. >After its successful introduction in 2006, the workshop on memory access takes place again this year. The sentences above from the Call for Papers for this workshop present the general topic in the new light of multicoreprocessors. Two years ago, at CF'06, the workshop has the more conventional title "Cache Optimization Strategies and Analysis Tools". This year's submissions were as interesting as two years ago, and we again chose four of them which, in our opinion, provide good coverage of the topic, and on the other hand, also make up for an interesting workshop. >Two of the papers focus on hardware solutions for best connection to memory modules, with the first concentrating on different parallel memory schemes, while the second evaluates heterogeneous memory architectures with different latencies and bandwidths in the same system. The other two papers show work on the software side, using modern multicore processors: how to optimize for data locality on NUMA multicore architectures with new OpenMP features, and how to reach good scalability and performance with new cache-oblivious algorithms on multicore. >In expectation of an exciting and discussion-loaded workshop at CF 2008 in Ischia.