The Architecture, Logic, and Circuit Design of a Bipolar, 200 Mbyte/sec, Serializing Data Mover IC, with 32-Bit TTL-Compatible Parallel I/O and Unique 1.8 Gbit/sec 'Cutoff Driver1 Differential PECL Serial I/O

摘要

This paper discusses the architecture, logic design, and circuit design of the Autobahn™ Spanceiver™- a serializing transceiver IC that facilitates movement of arbitrarily large blocks of 32-bit parallel TTL data at data rates up to 200 MBytes/sec, between two or more nodes on a shared, controlled-impedance , half-duplex, 1.8 Gbit/sec, differential-PECL serial channel.