Abstract: A novel architecture is proposed for future multi-terabit IP (internet protocol) routers, employing multiple cascaded stages of optical switching and buffering. WDM is used within the node to facilitate its operation. External synchronization is not required, and a void-filling algorithm is used to simplify hardware requirements. Packet priorities are not implemented in the current version of the switch, and the issue of header table lookup is not considered. Performance with respect to packet loss is studied by simulation, demonstrating that this multi-stage concept results in substantial hardware reduction.!11
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