The authors introduce a new sequential optimization paradigm based on the extraction of computational kernels, i.e., logic blocks whose behavior mimics the steady-state behavior of the original circuit. They present a procedure for the automatic extraction of such kernels directly from the gate-level description of the design. The advantage of this solution with respect to extraction algorithms based on STG analysis is that it can be applied to large circuits, since it does not require manipulation of the STG specification. They exploit computational kernels for optimization purposes; in particular, they describe an architectural decomposition paradigm whose template is reminiscent of the mux-based scheme adopted in parallel implementations of logic-level descriptions. They show the usefulness of the new optimization style by applying it to the problem of reducing the power dissipated by a sequential circuit. Experimental results, obtained on standard benchmarks, demonstrate the merit of the proposed approach.
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