Implementation of a P1619 crypto-core for Shared Storage Media

摘要

An alternative hardware implementation of a P1619 XTS-AES architecture, compared to the typical that have been proposed by now, is presented in this paper. The implementation is based on the use of two AES cores for simultaneous Tweak value calculation and block encoding/decoding operations. The implementation is efficient for burst mode of operation, decreasing by 25% the required time, exploiting pre-calculation of the tweak value. The overall performance satisfies the constraints for storage devices.