The MORRPH architecture is a general purpose reconfigurable processing unit, primarily designed to solve real time 2D image processing problems. Its robust architecture allows it to be used for other applications including 1D signal processing, 2D cellular automata problems, and 3D image processing. The modular, open ended architecture consists of an M/spl times/N rectangular mesh of processing elements (PEs), called the processing array. Each PE contains a single field programmable gate array (FPGA) chip and interconnections for several support chips. The FPGA chips within the PEs provide an array of logic resources, consisting of combinational logic functions, flip flops and internal chip routing resources. The types of support chips which are included in the PEs are not fixed, they are determined by the requirements of the computational task performed by the MORRPH. These memory, arithmetic, or processing support chips are specified and assembled on the MORRPH board for each particular application that is developed. Currently, the MORRPH architecture is implemented as an adapter card for the Industry Standard Architecture (ISA) computer bus. A constructed prototype with a 23 array of PEs is used in a current machine vision system to perform low level image processing functions. A significant performance increase is obtained by using the MORRPH as a preprocessing unit for the host processing computer. The MORRPH architecture is shown to be an inexpensive solution for relatively simple or very complex real time processing tasks.
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