Common processor element packaging for CHAMP

摘要

A generic approach for packaging advanced, application specific processors as well as future processing elements into a common JEDEC MCM (multi chip module) footprint is presented and demonstrated. Usage of a common I/O scheme at the MCM level eases future device upgrades, maximizes module reuse and minimizes redesign. An 11 chip, Xilinx XC4025 FPGA (field programmable gate array) based MCM was designed and built as a compute element using our CHAMP (Configurable Hardware Algorithm Mappable Preprocessor) architecture as a prototype for demonstrating the validity of the common processor element packaging strategy. We have conservatively estimated that for a wide range of solutions, the CHAMP MCM offers a cumulative 100:1 improvement in size, weight, power, cycle time and cost compared to state of the art, individually packaged DSPs and microprocessors on custom PCBs. The MCM design approach, implementation tradeoffs and experimental results for various measured performance parameters are also given.