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Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems

机译:自动化工具链以增强可重新配置多加速器系统的生产率

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Ease-of-use and faster implementation times are key challenges that the community has to face to extend the use of FPGAs to non-hardware experts. In this paper, these challenges are tackled by integrating ARTICo3 and IMPRESS tools to provide the users with a transparent way to build reconfigurable multi-accelerator systems. ARTICo3 is an integrated framework that provides an automated toolchain to generate a hardware-based processing architecture to transparently manage custom-made accelerators at runtime. IMPRESS is a reconfiguration tool for building highly-flexible reconfigurable systems. The integration of both tools results in an efficient reconfigurable design flow that decouples the implementation of reconfigurable accelerators from the implementation of an ARTICo3 static architecture that transparently distributes data to the accelerators. This static architecture is generated only once and reused in consecutive kernel implementations. This way, the user only needs to design the accelerators that are automatically implemented using interfaces compatible with the static architecture. From the user point of view, the reconfigurable fabric is a set of slots where accelerators can be transparently offloaded to decrease the workload on the processor. The integration of ARTICo3 and IMPRESS also allows building relocatable accelerators, thus reducing the overall memory footprint required for the partial bitstreams. Moreover, model-based design of accelerators using Simulink has also been included as an additional option for users with no hardware background to further simplify the use of reconfigurable systems. Experimental results show that the implementation time is improved by up to 2.96 × for a 4-slot reconfigurable system implementation with a memory footprint reduction of 4.54 ×.
机译:易用性和更快的实施时间是社区必须面临的关键挑战,以将FPGA的使用扩展到非硬件专家。在本文中,通过集成Artico3和令人印象深刻的工具来解决这些挑战,以便为用户提供一种透明的方式来构建可重新配置的多加速器系统。 Artico3是一个集成框架,提供自动工具链,以生成基于硬件的处理架构,以在运行时透明地管理定制的加速器。令人印象是建立高度灵活的可重新配置系统的重新配置工具。两种工具的集成导致有效的可重构设计流程,该流程将可重新配置的加速器的实现与透明地将数据分发给加速器的艺术品3静态架构的实现。此静态架构仅生成一次并在连续内核实现中重复使用。这样,用户只需要设计使用与静态架构兼容的接口自动实现的加速器。从用户的角度来看,可重新配置的结构是一组插槽,可以透明地卸载加速器以减少处理器上的工作负载。 Artico3的集成以及令人印象深刻允许构建可重定位的加速器,从而减少部分比特流所需的整体内存占点。此外,使用Simulink的基于模型的加速器设计也被包括为具有硬件背景的用户的附加选项,以进一步简化可重新配置系统的使用。实验结果表明,实施时间高达2.96倍,用于4时隙可重新配置系统实现,内存占地面积为4.54×。

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