Codesign of energy and resource efficient contention-free Network-on Chip for real-time embedded systems

摘要

Network-on-Chip (NoC) architectures increasingly gain attention of the academia and the industry, because of their excellent capabilities of Multiprocessor System-on-Chip building. This work presents a novel approach to application-specific irregular topology generation for contention-free and cost-efficient NoC. We take advantage of a priori known communication pattern to schedule computation and transmission as well as perform routing, taking into account time constraints of the system. The experiments confirm the superiority of our method over commonly used application-to-NoC mapping methodologies. Performance of the system is not deteriorated, while we observe significant resource savings.