300MHz to 500MHz Optimization of ARM Cortex M7 for Sensor Fusion SoCs by using Multi-threshold Libraries and Multi-bit Register cells in 16nm FinFET

摘要

Advanced technology nodes enable denser System on Chip (SoC) design at equivalent or higher performance, but at the cost of increased leakage. Designers use multi-threshold libraries and design optimizations like Multi-bit registers to optimize the Power, Performance, and Area (PPA) of the SoC. In this work, we demonstrate the PPA trade-offs involved in implementing the ARM Cortex M7 processor that is widely used in Sensor Fusion SoCs in TSMC’s 16nm FinFET technology. We show that use of multi-bank registers reduces design area by about 5%. So, the design can achieve 100MHz higher performance at iso-area by using Multi-bank registers. We also demonstrate that when a design is implemented at frequency targets higher than optimal (for a given technology), area and power consumption increase disproportionately.