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35 Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS

机译:35%在37 nm栅极长度PMOS上从凹陷 - SiGe排水延伸发生电流改善

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Results from the best reported PMOS transistor at a 37 nm gate length (Lg) built on a process with a recessed SiGe epitaxial layer are discussed. The process details include successful integration of SiGe at the drain extension (DE) location. A highly compressive SiGe layer, in close proximity to the channel, results in large hole mobility improvements. HRTEM based lattice parameter extractions confirm the compressive strain in the channel. In situ doped B in SiGe can be activated to a higher degree than implanted B in bulk Si resulting in further improvements from the lower DE resistance. Both changes combine to give an unprecedented 35% PMOS performance improvement. Process and device simulations that predict the observed parametric behavior quantitatively isolate the improvements to be ~ 28% from stress and 7% from DE resistance improvement.
机译:讨论了由基于凹陷SiGe外延层的过程的37nm栅极长度(LG)的最佳报告的PMOS晶体管的结果。过程细节包括在排水延长(DE)位置的SiGe成功集成。高度压缩的SiGe层,密切接近通道,导致大孔迁移率改进。基于HRTEM的晶格参数提取证实了通道中的压缩应变。在SiGE的原位掺杂B可以被激活到比植入B的植入B更高的程度,从而从较低的de电阻中进一步改进。这两种变化都结合起来给出前所未有的35%的PMOS绩效改进。预测观察到的参数行为的过程和设备模拟定量地将改进与应力的改善分离为约28%,并且从De抵抗改进的7%。

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