Development of a low-power field-programmable gate array using superconductor logic and semiconductor memory

摘要

We have been developing a superconductor-semiconductor hybrid field-programmable gate array (FPGA). The hybrid FPGA is designed asa combination of adiabatic quantum-flux-parametron (AQFP) logic circuits and complementary metal-oxide-semiconductor (CMOS)memory circuits, which takes advantages of both circuits: low-power dissipation of AQFP circuits and high-integration density of CMOScircuits. The feature of the hybrid FPGA is that the power dissipation of the CMOS memory can be reduced by driving the CMOS memorywith a low-voltage power source by utilizing the high sensitivity of AQFP circuits. The design and demonstration of a 2×2 hybrid FPGA arepresented, and the approach for the reduction of the power dissipation is discussed in this paper.