Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm

摘要

This paper describes the forwarded clock amplifier (FCA), phase interpolator (PI) and training algorithm used in receiver clocking of QuickPath Interconnect™ (QPI) in Intel® Core™ micro-processor, implemented in 45nm and 32nm process technologies. QPI is used for communication among processors/chipsets and delivers up to 25.6GB/s BW per port at 6.4GT/s. The FCA has a built in duty cycle corrector (DCC). Two PIs were used for each receiver lane to generate clocks to capture odd and even data independently. The novel training and retraining algorithm trains each PI for its corresponding data eye eliminating the need for any duty cycle correction of the PI output while maximizing the eye margin.