The authors describe a new configuration of the voltage-controlled CMOS resistor which is linear over a wide range of input voltage of both polarities. The new scheme tends to cancel the nonlinearity of the MOS transistor by a gate voltage control circuit. Simulation results show that the total harmonic distortion (THD) is less than 1% for a peak-to-peak differential input voltage of up to 10 V when the supply voltages V/sub DD/ =V/sub SS/ 5 V. An example of optimal design of the resistor is presented.
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机译：作者描述了一种用于电压控制的CMOS电阻的新配置，其在两个极性的宽范围内的线性上是线性的。 新方案倾向于通过栅极电压控制电路取消MOS晶体管的非线性。 仿真结果表明，当电源电压V / sub dd / = v / su / ss / 5v V / ss / 5v时，总谐波失真（THD）的峰值差分输入电压高达10V的峰值差分输入电压小于1％。 提出了电阻器的最佳设计示例。
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