A 2-D window processor for modular mage processing applications and its VLSI implementation

摘要

This paper presents the design and VLSI implementation of a 2-D windown processor that is capable of loading specific blocks (2-D windows) of the image spece, dependeing on a set of external control signals, onto any type of parallel architecture. The 2-D window is capable of moving along both dimensionsof the image space and to provide at its output the image data stored in it. Parallel architectures for image processing usually require a number of clock cycles in order to complete the specific tasks assigned to them by the host computer. The proposed processor takes advantage of this latency by preparing and loading the necessary data for the next operation of the parallel architecture while the architecture is still operating on the data of the previous operation. This is achieved through a predictor system, capable of predicting the position of the previous operation. This is achieved through a predictor system, capable of predicting the position of the next block of image that the parallel architecture will require, based on the history of the previous window movements. The processor was implemented in a VLSI chip using a 1mum CMOS Double Layer Metal (DLM) technology. The area of the chip, including the pads, is 6.102mmx4.845mm=29.56 mm~2 and the maximum frequency of operation, obtained after loaded simulations, ws found to be 41.67 MHz.