Towards Co-designing Neural Network Function Approximators with In-SRAM Computing

摘要

We propose a co-design approach for compute-in-memory inference for deep neural networks (DNN). We use multiplication-free function approximators based on $l1$ norm along with a co-adapted processing array and compute flow. Using the approach, we overcame many deficiencies in the current art of in-SRAM DNN processing, such as the need for DACs at each operating SRAM row/column, high precision ADCs, and limited support for multi-bit precision weights, and limited vector-scale parallelism. We also propose an SRAM-immersed successive approximation ADC (SA-ADC). We exploit the parasitic capacitance of bit lines of SRAM array as a capacitive DAC, allowing low area implementation of within-SRAM SA-ADC. Our $8imes 62$ SRAM macro requires a 5-bit ADC, achieves 105TOPS/W with 8-bit input/weight processing at 45 nm CMOS. We evaluated the performance of our proposed network for MNIST, CIFAR10, and CIFAR100 datasets. We chose a network configuration which adaptively mixes multiplication-free and regular operators. The network configurations utilize the multiplication-free operator for more than 85% operations from the total. The selected configurations are 98.6% accurate for MNIST, 90.2% for CIFAR10, and 66.9% for CIFAR100. Since most of the operations in the considered configurations are based on proposed SRAM macros, our compute-in-memory's efficiency benefits broadly translate to the system-level.