Fast In-Device Overlay Metrology on Multi-Tier 3DNAND Devices without DECAP and it's Applications in Process Characterization Control

摘要

Multilayer stack height in 3DNAND has reached the limit of the aspect ratio that etch technologies can cost-effectively achieve. The solution to achieve further bit density scaling is to build the stack in two tiers, each etched separately. While lowering the requirements on etch aspect ratio, stacking two tiers introduces a critical overlay at the interface between the stacks. Due to the height of each stack, stress- or etch-induced tilt in the channel holes is translated into overlay. Characterizing and controlling the resulting complex overlay fingerprints requires dense and frequent overlay metrology. The familiar electron beam metrology after etch-back (DECAP) is destructive and therefore too slow and expensive for frequent measurements. This paper will introduce a fast, accurate & robust data-driven method for In Device Overlay Metrology (IDM) on etched 3DNAND devices by making use of specially designed recipe setup targets. Also, potential applications for process control improvement will be demonstrated.