PWM Selection Method for High Performance of Two-Level Three-Phase Voltage Source Inverters in High Load Power Factor Ranges

摘要

In this paper, a pulse-width modulation (PWM) selection method for two-level three-phase voltage source inverters (VSIs) is presented to reduce the common-mode voltage (CMV) or the DC-link capacitor current (DCC) in high load power factor ranges. In general, the high CMV generates the large common-mode current, which causes electromagnetic emissions and motor damage. Also, the large DCC aggravates the lifespan and increases the size of the DC-link capacitors. Therefore, decreasing the CMV and DCC is necessary in the VSI systems. For this purpose, various PWM strategies, such as active zero-state PWM, near-state PWM, extended double-carrier PWM, and multi-carrier generalized discontinuous PWM, are reviewed. Furthermore, based on these PWM strategies, the PWM selection method is proposed to effectively reduce the CMV and DCC. The effectiveness of the PWM selection method is verified by simulation and experimental results with a permanent magnet synchronous motor drive system.