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Implementation of Post-processing for Phase-polarization Combined Modulation QKD System

机译:相位偏振组合调制QKD系统后处理的实现

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According to the characteristics of the combined modulation Quantum Key Distribution (QKD) system, a postprocessing method for phase-polarization combined modulation is designed and implemented, which is consist of sifting, parameter estimation, error reconciliation and privacy amplification. In this paper, we focuses on the research of error reconciliation. Firstly, the error reconciliation algorithm is given. On account of it, the hardware implementation scheme is designed and simulated on the Field Programmable Gate Array (FPGA) hardware platform. The error reconciliation algorithm mentioned above is based on Low Density Parity Check Code (LDPC) in IEEE802.16e standard. A fast iteration method is used in encoding scheme, on the basis of the check-matrix with sparsity as well as quasi-dual-diagonal structure, it reduces the quantity of logic resource and complexity of encoding and improves the encoding speed relatively. The encoder is implemented in FPGA with a 576-bit code length and 1/2 code rate. From the two aspects of functional and performance test, the system performance is higher than other implementations.
机译:根据组合调制量子密钥分布(QKD)系统的特性,设计和实现了一种用于相位偏振组合调制的后处理方法,包括筛选,参数估计,误差和解和隐私放大。在本文中,我们专注于纠结对帐的研究。首先,给出了错误协调算法。由于它,硬件实现方案是在现场可编程门阵列(FPGA)硬件平台上的设计和模拟。上面提到的误差协调算法基于IEEE802.16e标准中的低密度奇偶校验码(LDPC)。快速迭代方法用于编码方案,基于具有稀疏性以及准双对角线结构的校验矩阵,它降低了编码的逻辑资源数量和复杂性并提高了编码速度。编码器以FPGA实现,具有576位代码长度和1/2码速率。从功能性和性能测试的两个方面,系统性能高于其他实现。

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