A Compact Low-Power Mitchell-Based Error Tolerant Multiplier

摘要

Power consumption is a crucial design aspect in multimedia and machine learning applications. Approximate computing offers an energy-efficient approach for both power reduction and area optimization. In this paper, a hybrid approximation methodology based on error tolerant multipliers (ETMs) is introduced. The proposed design splits the approximation process into two parts: (1) approximating the most significant bits (MSBs) using approximate logarithms and (2) approximating the least significant bits (LSBs) using truncation. A prototype of the proposed multiplier is demonstrated with an image processing application (JPEG compression) using a Discrete Cosine Transform (DCT) where the power delay product (PDP) is improved by 1.9X. And the area utilization is reduced by 2.7X with only 20% reduction in the output image peak signal-to-noise ratio (PSNR).