Characterization of Digital IC for Sub-Nanosecond Dead-Time Adjustment Used in Synchronous DC-DC Converters

摘要

A digital integrated circuit for sub-nanosecond dead-time adjustment is characterized by time-domain measurements. The dead-time adjustment circuit (DTAC) generates two complementary signals for the switches used in synchronous DC-DC converter application. The control signals are generated from a PWM signal that is applied from a signal generator to the input of the DTAC. The circuit is based on a tapped delay-chain architecture and it is designed for frequencies up to 10 MHz. The DTAC is designed and fabricated in a 180-nm CMOS process. The characterization setup is shown and operating principle of the designed circuit is described. The generated dead times are measured for the whole range of the achievable discrete time-delay values at different switching frequencies.