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Low sidelobe level microstrip patch array: EM design and performance analysis

机译：低侧链级微带贴片阵列：EM设计和性能分析

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A high performance low-profile antenna array with low sidelobe level (SLL) and optimum beamwidth is in general preferred in several communication related applications. In this paper a planar microstrip array antenna with low SLL up to -20 dB and high gain performance is designed for 10 GHz. The dimensions of patch antenna is tapered to achieve low SLL. The results for patch array with individual feed and a common feed are presented.

机译：具有低侧倍细电平（SLL）和最佳波束宽度的高性能低调天线阵列在几种通信相关的应用中，通常优选。在本文中，设计了低于-20 dB的低SLL和高增益性能的平面微带阵列天线。贴片天线的尺寸是锥形的，以实现低SLL。提出了具有单独馈送的贴片阵列的结果和常用源。

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《IEEE Annual India Conference》|2016年|1 v.|共6页
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R. Manohar; Maumita Dutta; Hema Singh;
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中图分类计算技术、计算机技术;
关键词
Feeds; Microstrip antenna arrays; Microstrip; Microstrip antennas; Reflection; Antenna radiation patterns;

机译：饲料;微带天线阵列;微带;微带天线;反射;天线辐射模式;

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机译：具有极低旁瓣电平的低成本串联馈送微带天线阵列
4. Low sidelobe level microstrip patch array: EM design and performance analysis [C] . R. Manohar, Maumita Dutta, Hema Singh 2016 IEEE Annual India Conference . 2016

机译：低旁瓣级微带贴片阵列：EM设计和性能分析
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Low sidelobe level microstrip patch array: EM design and performance analysis

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