Performance analysis of seven level three phase asymmetric multilevel Inverter at various modulation indices

摘要

This paper analyses the performance of an asymmetric topology of three phase seven level Multi-Level Inverter (MLI) at various modulation indices. The ultimate aim of carrying out the analysis is to vary the modulation index so as to obtain an optimum value at minimum Total Harmonic Distortion (THD). This topology offers a major advantage such that it contains lower number of switches and input DC source as compared to the conventional and other existing three phase MLI topologies. Amongst the conventional topologies such as Diode Clamp Multi-Level Inverter (DCMLI), Flying Capacitor Multi-Level Inverter (FCMLI) and Cascaded Multi-Level Inverter (CMLI), CMLI requires minimum number of components as we go for higher number of levels. In case of seven level, three phase MLI's, conventional CMLI requires thirty six switches whereas in the proposed topology, the required number of switches are one third of the conventional CMLI i.e. only twelve switches are required for the generation of three phase seven level output voltage. For achieving this, Multi-carrier Sinusoidal Pulse Width Modulation (MSPWM) technique is used. The topology is successfully simulated and verified using Simu-link tool at various modulation indices and detailed comparison between modulation indices and THD thus obtained is also carried out.