The design considerations for implementing an optimized fixed-point space-vector pulse-width modulation (SVPWM) for a two-level inverter is presented. Most of the design simulations currently available are specified in floatingpoint precision to accelerate the process of verifying their functionality. However, area-optimized hardware implementation of these algorithms requires fixed-point precision. A generic function is formulated the precision required for each signal to get the desired precision. A non-convex optimization function is solved for the number of required bit-widths for the signals. This design has been implemented on an FPGA using the obtained solution in order to verify the resulting accuracy. The device utilization summary of this design is also compared to a floatingpoint precision design.
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