Cascaded seven level inverter with reduced number of switches using level shifting PWM technique

摘要

A multilevel inverter is a power electronic device that is used for high voltage and high power applications and has many advantages like, low switching stress, low total harmonic distortion (THD). Hence, the size and bulkiness of passive filters can be reduced. This paper proposes two new topologies of a 7-level cascaded multilevel inverter with reduced number of switches than that of conventional type which has 12 switches. The topologies consist of circuits with 9 switches and 7 switches for the same 7-level output. Therefore with less number of switches, there will be a reduction in gate drive circuitry and also very few switches will be conducting for specific intervals of time. The SPWM technique is implemented using multicarrier wave signals. Level Shifted triangular waves are used in comparison with sinusoidal reference to generate Sine PWM switching sequence. The number of level shifted triangular waves depends on the number of levels in the output. i.e. for n levels, n-1 number of carrier waves. This paper uses 1 KHz SPWM pulses with a modulation index of 0.8. The circuits are simulated using SPWM technique and the effect of the harmonic spectrum is analyzed. A comparison is made for the topologies with 9 switches and 7 switches and an effective reduction in THD has been observed for the circuits with less number of switches. The THD for 9 switches is 14% and the THD for 7 switches is 12.5%. The circuits are modeled and simulated with the help of MATLAB/SIMULINK.