Timing Analysis of Combinational circuits using Weights Binary Decision Diagram (WBDD)

摘要

Weights Binary Decision Diagram (WBDD) based timing analysis of combinational circuit is proposed. Here we express the combinational circuit as a directed graph. We compute and store the delay of combinational circuits for all combination of inputs for the range of delay values based on controlling values. Hence it is possible to look up the built in library and calculate the output delay of any combinational circuit. The output delay computation is much faster when compared to normal method of calculating the delay at each level of the combinational circuits. This can be used in the synthesis of network for low power consumption.