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Modeling and evaluating heterogeneous memory architectures by trace-driven simulation

机译:追踪仿真模拟和评估异构内存架构

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The issues behind the "memory wall" have existed for quite some time now, with realistic solutions still not available in modern processors. While the multicore approach will presumably fulfill the performance increase expected from Moore's Law in the near future, slow memory access will continue to remain a big obstacle and have a significant impact on the performance of applications. Even if a very fast path to off-chip memory was available, the optimal connection and hierarchical configuration of on-chip execution units and buffers would remain an open question, especially for general-purpose hardware. The goal of the workshop is to present latest research in how to overcome the problem of slow memory access with regard to an increasing number of cores on a chip. >After its successful introduction in 2006, the workshop on memory access takes place again this year. The sentences above from the Call for Papers for this workshop present the general topic in the new light of multicoreprocessors. Two years ago, at CF'06, the workshop has the more conventional title "Cache Optimization Strategies and Analysis Tools". This year's submissions were as interesting as two years ago, and we again chose four of them which, in our opinion, provide good coverage of the topic, and on the other hand, also make up for an interesting workshop. >Two of the papers focus on hardware solutions for best connection to memory modules, with the first concentrating on different parallel memory schemes, while the second evaluates heterogeneous memory architectures with different latencies and bandwidths in the same system. The other two papers show work on the software side, using modern multicore processors: how to optimize for data locality on NUMA multicore architectures with new OpenMP features, and how to reach good scalability and performance with new cache-oblivious algorithms on multicore. >In expectation of an exciting and discussion-loaded workshop at CF 2008 in Ischia.
机译:“记忆墙”背后的问题已经存在了一段时间,现在仍然没有现代处理器的现实解决方案。虽然多核方法可能会达到摩尔法在不久的将来预期的性能增加,但慢记忆进入将继续仍然是对应用的表现产生重大影响。即使可用的芯片内存的非常快速的路径可用,也可以是片上执行单元和缓冲区的最佳连接和分层配置将仍然是一个打开的问题,特别是对于通用硬件。研讨会的目标是提出最新研究,如何克服芯片上越来越多的内存访问问题。 >在2006年成功介绍后,记忆的研讨会今年再次进入。上面的句子从这个研讨会的论文的呼吁展示了众议议的多芯处理器中的一般话题。两年前,在CF'06,研讨会具有更传统的标题“缓存优化策略和分析工具”。今年的提交与两年前一样有趣,我们再次选择了其中的四个,我们认为,在我们看来,这是对主题的良好覆盖范围,另一方面还弥补了一个有趣的研讨会。 < P>两篇论文专注于硬件解决方案,以便最佳连接到内存模块,第一次集中在不同的并行内存方案上,而第二个在同一系统中评估具有不同延迟和带宽的异构内存架构。另外两篇论文在软件方面展示了软件,使用现代的多核处理器:如何在Numa多核架构上进行数据通道,具有新的OpenMP功能,以及如何在多核上的新高速缓存忘记算法达到良好的可扩展性和性能。 >期望在伊斯基亚省CF 2008的令人兴奋和讨论负载的车间。

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