FPGA Investigation on Error-Floor Performance of a Concatenated Staircase and Hamming Code for 400G-ZR Forward Error Correction

摘要

With a record 200Gbps 50-piece-FPGA implementation, we investigate performance of a concatenated-staircase-Hamming code proposed for OIF-400GZR. FPGA emulations reveal an error flare at 10-10BER lowering the predicted BER threshold from 1.25e-2 to 1.21e-2.