SysML Models Verification and Validation in an Industrial Context: Challenges and Experimentation

摘要

This paper presents a solution for SysML model verification and validation, with a return of experience from its implementation in an industrial context. We present this solution as a way to overcome issues regarding the use of SysML in an industrial context. We contribute by providing a method and a list of the existing challenges and experimentation results. We advocate the need to have semantics for SysML models without having to define a full domain-specific modeling language. We highlight the work, requirements and benefits that arise from the application of existing technical solutions, and hint at new perspectives and future development in system verification and validation.