As the technology scales into deep submicron regime, accurate estimate of interconnect parasitics has become one of important factors on path delay calculation. Design Compiler Topographical technology leverages the Synopsys physical implementation solution to derive the "virtual layout" of the design, thus the tool can accurately predict and use real net capacitances instead of statistical net approximations based on wire load models (WLM). A synthesis method based on WLM mode and topographical mode for 8051 micro-controller in 90 nm technology is presented in this paper. Results show that the Design Compiler Topographical technology can accurately predict post-layout timing and ensure closed correlation to the final physical design.
展开▼
